1. Field of the Invention
This invention relates to integrated electronic circuits. More particularly, it relates to small-geometry VLSI and ULSI circuits having multiple levels of metallic interconnects. The invention especially relates to a laser-alterable layer of metallization in an integrated circuit having multiple layers or levels of metallization.
2. Description of the Related Art
When fabricating Very Large Scale Integrated circuits and Ultra Large Scale Integrated circuits (VLSI and ULSI circuits) such as Dynamic Random Access Memory (DRAM) chips and Static Random Access Memory (SRAM) chips, it is often desirable to build redundancy into such circuits so as to increase the yield of acceptable chips. For example, a DRAM or SRAM chip might be designed to include one or more redundant rows or columns. During final testing of the chip, if a fault is detected it is desirable to be able to "wire around" the defect and thereby salvage what would otherwise be a defective chip.
As is well-known in the art, it is often possible to design a circuit such that "wiring around" a defect may simply be accomplished by breaking one or more electrical interconnects in the circuit. Using the techniques of the prior art, this has been accomplished in integrated circuits at the polysilicon (p-Si) level (layer 3 in FIGS. 1 and 2) most commonly by vaporizing a selected portion of the polysilicon using a laser. This technique necessitates the removal of the intervening layers of dielectric material (layers 4 and 6 in FIG. 1 and layers 4, 6, 8, 10, and 12 in FIG. 2) prior to the laser vaporization step. Masking, followed by wet chemical or plasma etching, is commonly used to remove the superimposed dielectric layers of silicon dioxide (layers 4 and 6 in FIG. 1 and layers 4, 6, 8, 10 and 12 in FIG. 2).
However, using the methods of the prior art, it is not possible to reliably etch down to the polysilicon layer and stop the etching exactly at the polysilicon/silicon dioxide interface. It is common practice to over-etch by approximately 10-20% so as to ensure substantially complete removal of the overlaying dielectric layers.
For integrated circuits having multiple metallization interconnect layers (as illustrated in FIG. 2) the etching techniques of the prior art jeopardize the integrity of the silicon substrate. This situation arises because, as the number of layers of metallization increases, the ratio of dielectric material above the polysilicon layer to dielectric material below that layer increases. Thus, for a given over-etch percentage, the absolute depth of the over-etch increases. This means that when an integrated circuit comprises multiple metallization layers it becomes increasingly likely that the oxide layer (layer 2 in FIGS. 1 and 2) which overlies the silicon substrate will be etched through, and thus at that locus, one no longer has single crystal silicon (c-Si) protected by an oxide layer. Moreover, since wet chemical etching is typically isotropic, the greater the number of layers which must be etched through to reach the polysilicon layer, the larger the cross-sectional area of the "window" or "hole" produced by the etching. As circuit density increases, this becomes more and more of a problem.
For the above reasons and for the sake of general convenience, it would be desirable to be able to laser-alter integrated circuits at the upper level of metallization inasmuch as this would greatly reduce the amount of etching required, especially for circuits having multiple metallization layers. Moreover, the uppermost layer of metallization is the most accessible interconnect layer. There are a number of reasons why laser-alteration of integrated circuits in their upper metallization layer has not been feasible in the past.
Metallization layers most commonly comprise aluminum which presents a number of difficulties for processes employing laser vaporization. In this regard it is interesting to compare the physical properties of polycrystalline silicon and aluminum, the materials which most often comprise the layers of an integrated circuit wherein the opportunity exists for laser alteration of the circuit. Whereas polycrystalline silicon melts at a relatively high temperature (melting point of Si=1410.degree. C.), aluminum melts at about 660.degree. C., a significantly lower temperature. In contrast, the boiling points of these two elements are virtually the same (2327.degree. C. versus 2355.degree. C.). Moreover, aluminum does not vaporize, even at high temperatures. Although judging from its relatively low melting point it might seem that aluminum would require less power to vaporize than polycrystalline silicon, aluminum's high boiling point and resistance to vaporization coupled with the reflective nature of aluminum in the portion of the spectrum where appropriate lasers emit necessitates the use of higher powers. It is contemplated that the need for high power levels, in conjunction with the relatively low melting point of aluminum, causes the metal to tend to splatter upon laser vaporization, potentially contaminating surrounding portions of the integrated circuit and possibly shorting other metallization lines in the vicinity of the laser-alteration site. Moreover, the aluminum interconnect lines in the metallization layer(s) are relatively wide and thick compared to the polycrystalline silicon interconnects. Thus, comparatively more material must be removed in the vaporization step of the process if alteration is to be performed in a metallization layer.
The present invention addresses this problem by providing a laminated metallization layer which comprises a refractory, conductive material which is less prone to splatter when an interconnect line of the material in the metallization layer is severed by laser vaporization. Using the process of the present invention allows one to design and build an integrated circuit which may be laser-altered in an upper layer of metallization, preferably the uppermost layer. This greatly reduces the extent of etching which is required in the methods of the prior art, thereby eliminating or greatly reducing the above-described problems associated with etching down to the polycrystalline silicon layer of an integrated circuit. Additionally, the present invention allows the laser-alteration of an integrated circuit by the removal of a relatively small volume of material. This reduces the chances of contaminating portions of the circuit in the vicinity of the laser-alteration site.